Détails du blog

1. Background and Industry Context

Rapid technological progress and the surging demand for high-efficiency smart products have further cemented the integrated circuit (IC) industry as a strategic pillar of national development. As the foundation of the IC ecosystem, semiconductor-grade monocrystalline silicon is central to both technological innovation and economic growth.

According to the International Semiconductor Industry Association, the global silicon wafer market recorded $12.6 billion in sales, with shipments reaching 14.2 billion square inches. Demand continues to rise steadily.

The industry is highly concentrated: the top five suppliers account for over 85% of global market share—Shin-Etsu Chemical (Japan), SUMCO (Japan), GlobalWafers, Siltronic (Germany), and SK Siltron (South Korea)—which underscores China’s heavy reliance on imported monocrystalline silicon wafers. This dependency is a key bottleneck constraining the country’s IC development. Strengthening domestic R&D and production capacity is therefore imperative.

2. Monocrystalline Silicon: Material Overview

Monocrystalline silicon underpins modern microelectronics; over 90% of IC chips and electronic devices are fabricated on silicon. Its dominance stems from several attributes:

• Abundance and Environmental Safety: Silicon is plentiful in the Earth’s crust, non-toxic, and environmentally friendly.

• Electrical Insulation and Native Oxide: Silicon naturally provides electrical insulation; upon thermal oxidation it forms SiO₂, a high-quality dielectric that prevents charge loss.

• Mature Manufacturing Infrastructure: Decades of process development have produced a deeply refined, scalable growth and wafer-fabrication ecosystem.

Structurally, monocrystalline silicon is a continuous, periodic lattice of silicon atoms—the essential substrate for chipmaking.

Process flow (high level): Silicon ore is refined to produce polycrystalline silicon, which is then melted and grown into a monocrystalline ingot in a crystal growth furnace. The ingot is sliced, lapped, polished, and cleaned to yield wafers for semiconductor processing.

Wafer classes:

• Semiconductor-grade: Ultra-high purity (up to 99.999999999%, “11 nines”) and strictly monocrystalline, with stringent requirements on crystal quality and surface cleanliness.

• Photovoltaic-grade: Lower purity (99.99%–99.9999%) and less demanding crystal-quality and surface specifications.

Semiconductor-grade wafers also demand superior flatness, surface smoothness, and cleanliness, increasing both process complexity and end-use value.

Diameter evolution and economics: Industry standards have progressed from 4-inch (100 mm) and 6-inch (150 mm) to 8-inch (200 mm) and 12-inch (300 mm) wafers. Larger diameters deliver more usable die area per process run, improving cost efficiency and reducing edge losses—an evolution driven by Moore’s Law and manufacturing economics. In practice, wafer size is matched to application and cost: for example, memory commonly uses 300 mm, while many power devices remain on 200 mm.

Through precise processes—photolithography, ion implantation, etch, deposition, and thermal treatments—silicon wafers enable a broad range of devices: high-power rectifiers, MOSFETs, BJTs, and switching components that power AI, 5G, automotive electronics, IoT, and aerospace—core engines of economic growth and innovation.

3. Monocrystalline Silicon Growth Technology

The Czochralski (CZ) Method

Proposed by Jan Czochralski in 1917, the CZ (crystal pulling) method efficiently produces large, high-quality single crystals from the melt. Today it is the dominant approach for silicon: approximately 98% of electronic components are silicon-based, and ~85% of those rely on CZ-grown wafers. CZ is favored for its crystal quality, controllable diameter, relatively fast growth rates, and high throughput.

Principle and equipment: The CZ process operates at high temperature in vacuum/inert conditions within a crystal growth furnace. Polycrystalline silicon is charged into a crucible and melted. A seed crystal contacts the melt surface; by precisely controlling temperature, pull rate, and the rotation of both seed and crucible, atoms at the melt–solid interface solidify into a single crystal with the desired orientation and diameter.

Typical process stages:

1. Tool Preparation & Loading: Disassemble, clean, and reload the furnace; remove contaminants from quartz, graphite, and other components.

2. Pump-down, Backfill & Melting: Evacuate to vacuum, introduce argon, and heat to fully melt the silicon charge.

3. Seeding & Initial Growth: Lower the seed into the melt and establish a stable solid–liquid interface.

4. Shouldering & Diameter Control: Expand to target diameter and maintain tight control via temperature and pull-rate feedback.

5. Steady Pulling: Sustain uniform growth at set diameter.

6. Termination & Cool-down: Complete the crystal, shut down, and unload the ingot.

Executed correctly, the CZ method yields large-diameter, low-defect monocrystalline silicon suitable for advanced semiconductor manufacturing.

4. Production Challenges and Directions

Scaling to larger diameters while preserving crystal perfection poses significant challenges, particularly in defect prediction and control:

• Quality Variability and Yield Loss: As diameter increases, the thermal, flow, and magnetic fields within the furnace become more complex. Managing these coupled multiphysics effects is difficult, leading to inconsistencies in crystal quality and lower yields.

• Control-System Limitations: Current strategies emphasize macroscopic parameters (e.g., diameter, pull rate). Fine-scale defect control still depends heavily on human expertise, which is increasingly inadequate for micro-/nano-scale IC requirements.